1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a semiconductor memory device having a divided word line structure (hierarchical word line structure) that a word line is divided into a main word line and a sub word line. More particularly, the present invention relates to a configuration for driving a sub word line to a selected state.
2. Description of the Background Art
FIG. 10 is a diagram schematically showing the configuration of an array portion of a conventional semiconductor memory device. In FIG. 10, in the memory cell array portion, memory cells MC are arranged in a matrix of rows and columns. Sub word lines SWL are arranged in correspondence to rows of memory cells MC. In FIG. 10, sub word lines SWL00, SWL01, SWL10, and SWL11 are representatively shown. Although not clearly shown, memory cells MC are divided into a plurality of memory blocks along the row direction (direction in which the sub word line extends). In each memory block, sub word line SWL is arranged in correspondence to a memory cell row, and memory cells MC in the corresponding row are connected to sub word line SWL.
In each memory block, a main word line ZMWL is arranged in correspondence to a predetermined number of sub word lines. Main word line ZMWL is arranged commonly to memory blocks aligned in the row direction.
In correspondence to sub word line SWL, a sub word driver SWD is arranged. In FIG. 10, sub word drivers SWD00, SWD01, SWD10, and SWD11 arranged in correspondence to sub word lines SWL00, SWL01, SWL10, and SWL11, respectively, are shown representatively.
Each of sub word drivers SWD00, SWD01, SWD10, and SWD11 drives a corresponding sub word line to a selected state in accordance with a signal potential on main word line ZMWL and a row selection signal RSL (sub decode signals SD and ZSD). Row selection signal RSL includes complementary sub decode signals SD and ZSD and designates one sub word line in a set of sub word lines arranged, in the column direction, in correspondence to one main word line. Specifically, in the layout shown in FIG. 10, according to sub decode signals SD and ZSD, one of sub word lines SWL00 and SWL10 is designated and one of sub word lines SWL01 and SWL11 is selected.
By disposing one main word line ZMWL in correspondence to a plurality of rows of memory cells MC, pitch condition on main word lines ZMWL is relaxed. To main word line ZMWL, only sub word drivers are connected, but memory cells MC are not connected. Therefore, the load on main word line ZMWL can be reduced, and a word line can be driven to the selected state at high speed. The configuration that the word line is divided into main word line ZMWL and sub word lines SWL (generically indicating sub word lines SWL00, . . . , and SWL11) is called a divided word line structure or hierarchical word line structure.
In FIG. 10, a bit line pair BLP arranged in correspondence to a column of memory cells is shown. Bit line pair BLP includes complementary bit lines BL and /BL, and a memory cell MC is connected to one of bit lines BL and /BL.
FIG. 11 is a diagram showing the configuration of sub word driver SWD illustrated in FIG. 10. In FIG. 11, sub word driver SWD includes: a P-channel MOS transistor (insulated gate field effect transistor) Q1 which is made conductive, when the signal potential on main word line ZMWL is at the L level (ground voltage Vss level), to transmit sub decode signal SD onto sub word line SWL; an N-channel MOS transistor Q2 which is made conductive, when the signal potential on main word line ZMWL is at the H level (high voltage Vpp level), to drive sub word line SWL to a non-selected state (ground voltage Vss level); and an N-channel MOS transistor Q3 which is made conductive, when complementary sub decode signal ZSD is at the H level (array power supply voltage Vdda level), to drive sub word line SWL to a non-selected state (ground voltage Vss level).
Sub decode signal SD changes between a high voltage Vpp and a ground voltage Vss, and complementary sub decode signal ZSD changes between an array power supply voltage Vdda and ground voltage Vss. High voltage Vpp is higher than array power supply voltage Vdda. High voltage Vpp is supplied to a selected sub word line SWL by sub decode signal SD for the following reason.
As shown in FIG. 11, each memory cell MC includes a memory capacitor MQ for storing information and an access transistor MT which is made conductive, in response to the signal potential on sub word line SWL, to connect memory capacitor MQ to a corresponding bit line BL (or /BL). Access transistor MT is formed of an N-channel MOS transistor. The voltage level of H-level data transmitted to bit lines BL and /BL is the array power supply voltage Vdda level. In the case of writing H-level data to memory capacitor MQ, it is therefore necessary to prevent that the voltage level of the H-level data in memory capacitor MQ drops due to a threshold voltage loss in access transistor MT for the following reasons:
(i) At the time of reading memory cell data, a sufficiently large voltage change has to be brought about on a corresponding bit line.
(ii) A voltage applied to the main electrode (cell plate electrode) of a memory capacitor is usually an intermediate voltage between the array power supply voltage and the ground voltage, and a precharge voltage on a bit line is similarly at the intermediate voltage level. Consequently, by equaling a bit line voltage change when H-level data is read on a corresponding bit line with that when L-level data is read, a sense margin of a not-shown sense amplifier is increased.
(iii) A sufficient amount of charges is accumulated in memory capacitor MQ, to prevent the stored information from being lost due to a leak current or the like. A sense amplifier is arranged in correspondence to each bit line pair and activated to amplify the difference between voltages of bit lines in a corresponding pair.
In order to prevent the threshold voltage loss in voltage level of the H-level data, high voltage Vpp higher than array power supply voltage Vdda is supplied onto a selected sub word line SWL. Main word line ZMWL is set to the high voltage Vpp level in a non-selected state for the reason that even if sub decode signal SD at the high voltage Vpp level is applied, in sub word driver SWD, P-channel MOS transistor Q1 is set in the off state with reliability to hold the corresponding sub word line SWL in the non-selected state.
In the configuration of sub word driver SWD shown in FIG. 11, when main word line ZMWL is at the high voltage Vpp level, MOS transistor Q1 is in the off state and MOS transistor Q2 is in the on state. In this state, since MOS transistor Q1 is in the off state and MOS transistor Q2 is in the on state, irrespective of the logic level of each of sub decode signals SD and ZSD, sub word line SWL is driven to the ground voltage Vss level. Therefore, when main word line ZMWL is at the high voltage Vpp level in the non-selected state, corresponding sub word line SWL is held at the ground voltage Vss level or the non-selected state.
On the other hand, when main word line ZMWL is driven to the selected state at the ground voltage Vss level, MOS transistor Q1 is turned on or off, and MOS transistor Q2 is turned off. When sub decode signal SD is at the high voltage Vpp level, MOS transistor Q1 is turned on and sub decode signal SD at the high voltage Vpp level is transmitted to sub word line SWL.
On the other hand, when sub decode signal SD is in the non-selected state at the ground voltage Vss level, the gate and source of MOS transistor Q1 become at the same voltage level and MOS transistor Q1 is turned off. In this state, both MOS transistors Q1 and Q2 are in the off state. Sub decode signal ZSD is at the array power supply voltage Vdda level at this time, and MOS transistor Q3 is turned on to drive not-selected sub word line SWL to the ground voltage Vss level. That is; by using complementary sub decode signals SD and ZSD, sub word line SWL is prevented from entering a floating state, and a non-selected sub word line SWL is held at the ground voltage Vss level with reliability.
FIG. 12 is a diagram showing the configuration of a conventional sub decode signal generating portion. In FIG. 12, the sub decode signal generating portion includes: a sub decoder 900 for generating a sub decode first signal ZSDF in accordance with a predecode signal Z; and a sub decode signal generating circuit 910 for generating a complementary sub decode signal (row selection signal) from sub decode first signal ZSDF.
Sub decoder 900 includes: a P-channel MOS transistor 901 connected between a high voltage node receiving high voltage Vpp and a node 902, and receiving a reset signal ZRSET at a gate thereof; and an N-channel MOS transistor 903 connected between node 902 and a ground node, and receiving predecode signal X at a gate thereof. Reset signal ZRSET changes between high voltage Vpp and ground voltage Vss.
Predecode signal X changes between a peripheral power supply voltage Vddp and ground voltage Vss. Predecode signal X is generated by predecoding a predetermined bit in a row address signal. For example, in the case where two sub word lines are arranged in correspondence to one main word line as shown in FIG. 10, predecode signal X is generated by predecoding one bit of a row address signal.
Sub decode first signal ZSDF changes between high voltage Vpp and ground voltage Vss.
Sub decode signal generating circuit 910 includes: an inverter 911 for receiving sub decode first signal ZSDF and generating sub decode signal SD; an inverter 912 for receiving sub decode first signal ZSDF; and an inverter 913 for receiving an output signal of inverter 912 and generating complementary sub decode signal ZSD.
Inverter 911 receives high voltage Vpp as an operation power supply voltage, and inverters 912 and 913 receive array power supply voltage Vdda as an operation power supply voltage. Therefore, sub decode signal SD has an amplitude of the high voltage Vpp level, and complementary sub decode signal ZSD has an amplitude of the array power supply voltage Vdda level.
The operation of the sub decode signal generating portion shown in FIG. 12 will now be described briefly.
In a standby state, reset signal ZRSET is at the ground voltage Vss level, and predecode signal X is at the ground voltage Vss level. Node 902 is therefore charged to the high voltage Vpp level by MOS transistor 901 that is in the on state.
Therefore, sub decode first signal ZSDF is at the high voltage Vpp level, sub decode signal SD is at the L level of the ground voltage level, and complementary sub decode signal ZSD is at the H level of the array power supply voltage Vdda level. Consequently, in sub word driver SWD shown in FIG. 11, MOS transistor Q3 is in the on state, main word line ZMWL is at the high voltage Vpp level, and sub word line SWL is maintained at the ground voltage level.
When an active cycle of selecting a memory cell is started, reset signal ZRSET turns high voltage Vpp level, and MOS transistor 901 is turned off. When predecode signal X is in the selected state, it attains the H level of the peripheral power supply voltage Vddp level, MOS transistor 903 is turned on, and sub decode first signal ZSDF from node 902 is driven to the ground voltage Vss level. Accordingly, sub decode signal SD attains the high voltage Vpp level, and complementary sub decode signal ZSD attains the ground voltage Vss level.
On the other hand, in the non-selected state, predecode signal X is at the ground voltage level. MOS transistor 903 is in the off state, and node 902 maintains the high voltage level set in the standby state. Although not shown in FIG. 12, a P-channel MOS transistor for latching node 902 at the high voltage Vpp level in the non-selected state is arranged for node 902. In the active cycle for selecting a memory cell, therefore, output signal ZSDF of not-selected sub decoder 900 is reliably held at the high voltage Vpp level in the non-selected state.
By setting the amplitude of complementary sub decode signal ZSD at the array power supply voltage Vdda, power consumption is reduced as compared with the case of using a complementary sub decode signal having an amplitude of the high voltage Vpp level. In addition, by using stable array power supply voltage Vdda, the voltage level of complementary sub decode signal ZSD is stabilized.
FIG. 13 is a signal waveform diagram representing the operation of sub decode signal generating circuit 910 illustrated in FIG. 12. Referring to FIG. 13, the operation of sub decode signal generating circuit 910 shown in FIG. 12 will now be described.
The amplitude of an input signal (sub decode signal SD) of inverter 912 is at the high voltage Vpp level and is larger than that of an output signal of inverter 912. Consequently, an input logic threshold voltage of inverter 912 is set to be relatively high. By setting the input logic threshold voltage to be relatively high, the rising and the falling times of the output signal are made equal with respect to a change in the input signal of inverter 912.
In the standby state, sub decode first signal ZSDF is at the H level which is the high voltage Vpp level. Consequently, sub decode signal SD is at the L level which is the ground voltage level, and sub decode signal ZSD is at the H level which is the array power supply voltage level.
When a memory cycle is started, the address of a corresponding sub word line is designated, and sub decode first signal ZSDF lowers from the high voltage Vpp level to the ground voltage level at time T0, inverter 911 drives sub decode signal SD to the high voltage Vpp level at high speed. This is because CMOS transistors are used for inverter 911, and generally, the current driving power of a MOS transistor increases as the gate voltage thereof increases in absolute value.
On the other hand, in response to the falling of sub decode first signal ZSDF, inverter 912 raises its output signal to the H level at time T1. Inverter 912 uses array power supply voltage Vdda as an operation power supply voltage, and therefore, the current driving capability of inverter 912 is lower than that of inverter 911. Thus, an output signal of inverter 912 changes relatively slowly as compared with an output signal of inverter 911.
When the voltage level of the output signal of inverter 912 becomes higher than the input logic threshold voltage of inverter 913, the voltage level of complementary sub decode signal ZSD from inverter 913 drops and reaches the ground voltage level at time T2. Inverter 913 also uses the array power supply voltage as an operation power supply voltage, and therefore, output driving capability of inverter 913 is lower as compared with inverter 911, and a change of the input signal of inverter 913 is relatively slow. Consequently, complementary sub decode signal ZSD from inverter 913 changes with a certain delay from the output signal of inverter 911 and attains the ground voltage level at time T2.
As shown in FIG. 13, therefore, because of the delay time in inverter 913, during a period Ta from time T1 to time T2, both sub decode signals SD and ZSD are at the H level. When main word line ZMWL is in the selected state for the period Ta in sub word driver SWD shown in FIG. 11, as shown in FIG. 14, a through current flows via MOS transistors Q1 and Q3, and current consumption increases. Since MOS transistor Q3 is in the on state until sub decode signal ZSD becomes equal to or lower than the threshold voltage Vth, the period in which the through current flows is actually longer than period Ta.
In a normal operation mode, when high voltage Vpp is consumed by the through current and further, there is a possibility that the voltage level of high voltage Vpp drops, and accordingly the voltage level of selected sub word line SWL drops. Under such situation, data of the H level at a sufficient voltage level could not be written to a memory cell. In addition. H-level data stored in a memory cell could not be read out onto the corresponding bit line at high speed. Consequently, the memory cell data could not be sensed and amplified accurately by a not-shown sense amplifier, so that an accurate memory operation cannot be guaranteed.
Particularly, in an accelerated test mode such as wafer burn-in test, all the word lines (sub word lines) or half of sub word lines, that is, sub word lines of odd-number or even-number addresses are simultaneously selected. In the case that a plurality of sub word lines are simultaneously selected, sub word lines greater in number than those in the normal operation mode are selected, charges supplied from the high voltage generating circuit are consumed more, and the degree of drop of high voltage Vpp becomes greater. This is because the number of selected sub word lines increases and the number of paths of the through current increases. In the case where all of charges supplied from the high voltage generating circuit or more are consumed due to such a through current, the voltage level of high voltage Vpp is kept at the dropped level, a high voltage at an intended level cannot be applied to selected word lines (main and sub word lines), a voltage stress cannot be applied accurately. Consequently, such a problem arises that the reliability of a product (chip) cannot be assured even if a burn-in test is carried out.
An object of the invention is to provide a semiconductor memory device in which a through current is not caused in a sub word driver in selecting a word line.
Another object of the invention is to provide a semiconductor memory device capable of driving a selected sub word line to a predetermined voltage level at high speed with accuracy.
Further object of the invention is to provide a semiconductor memory device with reduced power consumption.
A semiconductor memory device according to a first aspect of the invention includes: a first decoding circuit for generating a sub decode first signal for specifying one of sub word lines arranged in correspondence to a main word line in accordance with an address signal; a first driving circuit receiving a first voltage as an operation power supply voltage and generating a first sub decode signal in accordance with the sub decode first signal; a second driving circuit receiving a second voltage as an operation power supply voltage and generating an internal sub decode signal in accordance with the sub decode first signal; and a gate circuit receiving the second voltage as an operation power supply voltage and generating a second sub decode signal complementary to the first sub decode signal in accordance with output signals of the first and second driving circuits. One sub word line is designated in accordance with a set of the first and second sub decode signals.
A semiconductor memory device according to a second aspect of the invention includes: a plurality of memory cells arranged in rows and columns; a plurality of sub word lines arranged in correspondence to the memory cell rows and each having memory cells of a corresponding row connected; a plurality of main word lines each arranged in correspondence to a predetermined number of sub word lines; a main word line selecting circuit for driving one of the plurality of main word lines to a selected state in accordance with a first address signal; a sub decode circuit for generating a sub decode first signal for selecting one of the predetermined number of sub word lines in accordance with a second address signal; and a sub decode driving circuit for generating a pair of complementary sub decode signals in accordance with the sub decode first signal. The sub decode driving circuit includes: a first driving circuit receiving a first voltage as an operation power supply voltage and generating a first sub decode signal in accordance with the sub decode first signal; a second driving circuit receiving a second voltage as an operation power supply voltage and generating an internal sub decode signal in accordance with the sub decode first signal; and a gate circuit receiving the second voltage as an operation power supply voltage and generating a second sub decode signal complementary to the first sub decode signal in accordance with output signals of the first and second driving circuit. One of the predetermined number of sub word lines is designated in accordance with the first and second sub decode signals
The semiconductor memory device according to the second aspect of the invention further includes a sub word driver arranged in correspondence to the respective sub word lines, for driving a corresponding sub word line to a selected state in accordance with a signal on a corresponding main word line and a pair of complementary sub decode signals from the sub decode driving circuit.
By generating the second sub decode signals in accordance with output signals of the first and second driving circuits, the second sub decode signal can be changed at high speed in response to a change in the first sub decode signal. The period in which both complementary first and second sub decode signals are in the state where a through current flows in a corresponding sub word driver can be shortened, and accordingly current consumption can be reduced. In addition, a signal at a predetermined voltage level can be transmitted to a selected sub word line with reliability, and the selected sub word line can be reliably driven to the selected state at the predetermined voltage level.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.